1. Field of the Invention
The field of the invention relates to voltage level shifters for shifting the voltage level between two different voltage domains.
2. Description of the Prior Art
It is known to provide voltage level shifters to convert a signal from one voltage domain to a signal suitable for another voltage domain. This allows circuits that operate different voltage levels to interface with each other.
In the design of Application Specific Integrated Circuits (ASIC), circuit design is often performed via the implementation of Standard Cells. In this way ASIC manufacturers can create functional blocks with known electrical characteristics such as propagation delay, capacitance and inductance that can be represented in third party circuit design tools. Standard Cell design is the utilisation of these functional blocks to achieve high gate density and good electrical performance. Accordingly the constraints on circuit components (e.g. electrical characteristics) for use in Standard Cell design are carefully controlled.
Known voltage level shifters for inclusion in Standard Cell design typically comprise dual voltage NWELL architectures that are costly to fabricate and consume a comparatively large circuit area. A problem with known Standard Cell library level shifters are that they have a larger than ideal area, have high leakage current and having slow voltage-shift response time. There is no known implementation of a voltage shifter having a single NWELL that is practically possible for implementation in a Standard Cell library.
Accordingly there is a need for voltage level shifter suitable for employing in a Standard Cell Library that has reduced area, reduced leakage, faster response time and is more cost-effective to fabricate.
FIG. 1 schematically illustrates a known voltage level shifter as employed in a Standard Cell Library. The circuit of FIG. 1 comprises a plurality of Complementary Metal Oxide Semiconductor (CMOS) transistors and comprises two NWELLs. The Standard Cell of FIG. 1 is a double height cell due to the fact that there is a separate isolated NWELL of the PMOS of the pass transistor of this circuit. The Standard Cell of FIG. 1 is a circuit 100 comprising a PMOS transistor 102 where the transistor source is connected to a low voltage domain (VDDL) and the transistor drain is connected to the drain of an NMOS transistor 104 whose source is connected to the ground voltage. The gate of the NMOS transistor 104 is connected an input voltage Vin_L which can either be at logic level zero or logic level 1. The PMOS transistor 102 and the NMOS transistor 102 together represent a first isolated NWELL of the circuit 100.
A second (separate) NWELL is formed in the circuit of the Standard Cell 100 by a set of four PMOS transistors 106, 108, 110, 112. The sources of PMOS transistors 106 and 108 are connected to a high voltage domain VDDH. In addition to the four PMOS transistors 106, 108, 110, 112, there are a further two NMOS transistors 114, 116 which complete a sub-circuit of a total of six transistors that are connected between the high voltage domain VDDH and a ground potential voltage line 117. In this six-transistor sub-circuit, the gates of the PMOS transistor 106 and NMOS transistor 114 are connected to the input voltage Vin_L, whilst the gates of the PMOS transistor 108 and NMOS transistor 116 are connected to a circuit node 152 situated between the drains of the PMOS 102 and the NMOS 104 of the first NWELL.
The PMOS transistors 110 and 112 are cross-coupled in the sense that the gate of PMOS transistor 112 is connected to the drain of NMOS transistor 114 whilst the gate of PMOS transistor 110 is connected to a node 156 connecting the drains of the transistors 116 and 112. The output of the Standard Cell 100 Vout_H is provided via a signal path comprising a first inverter 118 and a second inverter 120 connected in series. The reason that two NWELLs are required in the circuit 100 is that it is necessary to keep the NWELL of the pass transistor PMOS 102 separated from the regular NWELL formed by the transistors 106, 108, 110, 112. In fact, it is desirable to keep the body of the PMOS transistor 102, whose source is connected to the low voltage domain VDDL, at the same corresponding source potential level i.e. VDDL. Otherwise, if the substrate of the PMOS transistor 102 were kept in the regular voltage domain VDD, then the body-to-source potential of the PMOS 102 would increase due to the so-called “body effect” of the transistor and as a consequence the threshold voltage of the PMOS transistor 102 would increase. Note that the PMOS 102 conducts when the voltage between the gate and the source is less than the threshold voltage Vt. Accordingly, a high threshold voltage Vt would have a consequence that it would be difficult to switch off the PMOS transistor 102. This situation is undesirable. Hence the body of the PMOS 102 is maintained at the low source voltage level VDDL by isolating the two transistors 102 and 104 in a separate NWELL.
The dual NWELL structure of the circuit 100 and the double height cell mean that the area of the cell is large and costly to fabricate. The Standard Cell circuit 100 also consumes a large amount of power and has significant current leakage.
In the circuit of FIG. 1, when the input voltage Vin_L corresponds to a logical zero, in the first NWELL the NMOS transistor 104 is off whilst the PMOS transistor 102 is switched on. In the second NWELL, when the input voltage is a logical zero, the NMOS transistor 114 and the PMOS transistor 112 both switch off so that the node 154 is at the higher voltage domain VDDH whereas the node 156 is at zero voltage. However, the PMOS transistor 108 is metastable when the input voltage is a logical zero, which means that the output of the pass transistors 102 and 104 is not reliably isolated from the higher voltage domain VDDH. Accordingly, the node 156 is at an indefinite voltage and thus corresponds to only a so-called “weak zero” voltage. This problem with the metastability of the PMOS transistor 108 for the circuit 100 occurs only in the circumstance where the input voltage corresponds to a logical zero. When the input voltage Vin_L corresponds to a logical 1 in the circuit of FIG. 1, the transistors 106, 110, 116 and 102 all switch off reliably whilst the transistors 114, 104, 108 and 112 are all switched on and the output voltage Vout_H corresponds to the high voltage domain VDDH.
Thus in the known Standard Cell voltage level shifter circuit of FIG. 1, there is a problem of ensuring the correct operation of the pass transistors 102 and 104 of the first NWELL that can arise due to metastability of one of the transistors in the switching circuit i.e. PMOS transistor 108. This problem arises when the input voltage has a logic level zero. Furthermore, it is desirable to provide a Standard Cell voltage level shifter that has reduced area and reduced leakage current relative to the circuit 100 of FIG. 1.
FIG. 2 schematically illustrates a known single NWELL voltage level shifter for use in a dual-supply voltage design described in the search paper “Level Conversion for Dual-Supply Systems” by Fujio Ishihara and Farhana Sheikh, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, volume 12, no. 2, February 2004. The circuit of FIG. 2 is a diode based single well voltage level shifter but this single NWELL circuit does not comply with the strict requirements of a Standard Cell voltage level shifter. The diode-based design of FIG. 2 can only work in an input/output circuit where there is the option to use thick oxide and higher voltage transistors. Previously known topologies for single NWELL voltage level shifters are simply not practical for use in a Standard Cell library of very deep sub-micron technology due to their physical properties.
The single NWELL circuit 200 of FIG. 2 comprises an NMOS pass transistor 210 whose source is connected to the input voltage Vin_L and whose drain is connected to a circuit node 250. The circuit 200 further comprises a PMOS transistor 212 whose source is connected to a high voltage domain VDDH and whose drain is connected to the drain of an NMOS transistor 214. The source of the transistor 214 is in turn connected to a ground voltage. The circuit 200 comprises a fourth CMOS transistor, which is a PMOS transistor 216 whose source and drain are connected between the high voltage domain VDDH and the node 250 and whose gate is connected to a further circuit node 252 on an output line of the circuit 200. The signal passes through a single inverter 218 prior to being output as Vout_H.
In the circuit 200, when the input voltage Vin_L corresponds to a logical zero the pass transistor 210 is switched and the PMOS transistor 212 is also switched on. For logical zero input, the NMOS transistor 214 is strongly off but the PMOS transistor 216 is only weakly off (i.e. it is metastable). Due to the metastability of the PMOS transistor 216, the node 252 does not have a well-defined voltage and this node will initially be at a voltage of zero before rising to the high voltage level VDDH. After passing through the inverter 218, the output voltage will be zero. The metastabilty of the PMOS transistor 216 also results in a higher level of leakage current than would be the case if there were no metastability in the circuit 200. Due to the metastability of the PMOS transistor 216, there is also a problem with a poorly defined voltage level at the node 250 at the output of the pass transistor 210.
When the input Vin_L to the circuit 200 of FIG. 2 corresponds to a logical one all of the transistors 210, 214 216 are switched on whereas the PMOS transistor 212 whose gate is connected to the node 250 is off, but only weakly off. Thus the transistor 212 is metastable in this situation. This gives rise to a uncertain voltage at the node 250 which should be at a high voltage level VDDH but in fact is only weakly at the desired voltage level. The voltage level at the node 252 should be zero so that the voltage at the output of the inverter 280 should correspond to VDDH. The circuit of FIG. 2 corresponds to only a half-feedback circuit. As explained above, there are problems caused by the metastability of some of transistors 216 and 212 for voltage inputs of logical zero and logical one respectively. For a more efficient operation of the voltage level shifter of FIG. 2, it is desirable that the node 250 should be at a stronger zero voltage for an input voltage of logical zero. This would reduce leakage current of the system.
Circuit 200 of FIG. 2 corresponds to so called half-latch circuit and causes the circuit 200 to malfunction for an input voltage of logical zero. When the input voltage Vin_L is a logical 0 then the node 250 is driven by the NMOS pass transistor 210 and a further NMOS transistor (not shown in FIG. 2) that drives the input Vin_L. Both of these two NMOS transistors will be very weak as a result of the difference between the gate to source voltage Vgs and the threshold voltage Vt will be small and closer to zero. This will mean that the two NMOS transistors including the transistor 210 will not be in the desired “linear region” of the transistor. In the linear region the gate to source voltage Vgs exceeds the threshold voltage Vt and the body to source voltage Vbs is less than the difference between Vgs and Vt. As a result of this instability, the single NWELL voltage shifter of FIG. 2 cannot be employed in the Standard Cells library of deep sub micon technology. Furthermore, in the so-called “FF corner” corresponding to fast NMOS and fast PMOS transistors and high temperature corners where leakage current is likely to be high, then the potential of the node 250 of FIG. 2 is likely to become non-zero even for a logical input of zero due to the high resistive path between the input voltage Vin_L and the node 250. As a consequence, the PMOS transistor 212 would likely go into a “triode region” (i.e. a linear region) which will weaken the logic of the node 252 at the output of the circuit 200.
Thus there is a requirement for a voltage level shifter such as a single NWELL design for use in Standard Cells that consumes less area and is more cost effective to fabricate yet which is stable for inputs of both logical zero and logical 1.